Series read-only-memory having capacitive bootstrap precharging circuitry
US4570239A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 1983 |
| Grant date | Feb 11, 1986 |
| Priority date | — |
| Expiry date | Jan 24, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read-only-memory (ROM) having a plurality of enhancement and depletion transistors selectively arranged in an array with the gates of the transistors in each row connected in common to form word lines, and the current paths of the transistors in each column connected in series to form bit lines. The word lines are precharged and then allowed to float. The bit lines are then precharged, bootstrapping the word lines above the precharge level. A selected one of the word lines is thereafter discharged before one end of each of the bit lines is connected to ground. A selected bit line will either remain precharged or be discharged depending upon the type of transistor at the intersection of the selected word and bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.