Semiconductor device
US4571607A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 26, 1984 |
| Grant date | Feb 18, 1986 |
| Priority date | — |
| Expiry date | Jan 26, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The capacity of a capacitor constituted by a metal-insulator-semiconductor layer configuration varies depending on the quantity of electric charge staying in the neighborhood of the interface between the insulating layer and the semiconductor layer. Because interleaving of a thin semiconductor layer between the insulating layer and the semiconductor layer to form a P-N junction therebetween is effective to confine some quantity of electric charge in the thin semiconductor layer, the capacity of the capacitor can be regulated. When the quantity of electric charge confined in the thin semiconductor layer is given in the form of an electric pulse signal, the signal can be memorized in the form of capacity. A layer configuration of a conductor, an insulator and a semiconductor, including a P-N junction therein fabricated on a substrate with which the layers are isolated, functions as a memory cell which consists of only one capacitor and, which requires an extremely small area of a chip, and which is involved with non destructive read out. The same layer configuration is effective to function as a photoelectro transducer or an image sensor unit, when the conductor layer is fabricated w…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.