CMOS Logic circuits with all pull-up transistors integrated in separate chip from all pull-down transistors
US4572972A · kind A · utility
13Cited by
7References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 18, 1983 |
| Grant date | Feb 25, 1986 |
| Priority date | — |
| Expiry date | Jan 18, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip with a preferred ground structure and including only pull-down transistors (on-chip) is operated by means of an off-chip pull-up transistor arrangement for precharging the data bus to logic high. The arrangement exhibits relatively low noise characteristics allowing relatively high frequency operation without generating noise voltages which exceed FET threshold voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.