Unitary phase and frequency adjust network for a multiple frequency digital phase locked loop
US4573017A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 3, 1984 |
| Grant date | Feb 25, 1986 |
| Priority date | — |
| Expiry date | Jan 3, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A unitary phase and frequency adjust network for use in a multiple frequency digital phase-locked loop circuit is described. The unitary phase and frequency adjust network utilizes a single circuit to effect both phase and frequency adjustments. The multiple frequency digital phase-locked loop effects phase adjustments by selectively combining or subtracting a reference clock signal with a derived programmable clock signal thereby generating a composite digital phase-locked loop clock signal. The phase and frequency adjust network effects frequency shifts by selectively adding or subtracting pulses from the composite clock signal at a rate determined by a programmably controlled clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.