Method for making a high performance transistor integrated circuit
US4573256A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1983 |
| Grant date | Mar 4, 1986 |
| Priority date | — |
| Expiry date | Aug 26, 2003 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/01
Abstract
A process for making high performance NPN bipolar transistors functioning in a current switch logic circuit. A bipolar transistor is formed within an isolated region of a monocrystalline silicon body. The transistor includes an N+ subcollector, and N+ collector reach-through which connects the subcollector to a major surface of the silicon body, a P base region above the subcollector and adjacent to the reach-through an N+ emitter region within the base region and extending from the major surface. The base region includes an intrinsic base region located below the emitter region and an extrinsic region extending from the major surface and adjacent to the emitter region. The extrinsic base completely surrounds the emitter region. A mask is formed above the major surface having openings only above major portions of the extrinsic base regions. A P+ region is formed in the extrinsic base region by ion implanting with a P type dopant to a depth less than the depth of the N emitter region followed by a short thermal anneal to activate the P dopant. Electrical ohmic contacts are made and the elements are connected in a current switch logic circuit. The use of high conductivity P+ region i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.