Memory cell and array
US4574367A · kind A · utility
0Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 10, 1983 |
| Grant date | Mar 4, 1986 |
| Priority date | — |
| Expiry date | Nov 10, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fall-through memory array comprising in a plurality of rows and columns a plurality of memory cells, each memory cell comprising a pair of cross-coupled transistors having three emitters, a collector and a base. Control potentials applied to a word line, coupled to each one of two of the emitters of each of the transistors, control the transfer of data bits from one row of such memory cells to another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.