Control circuit for an integrated device
US4575642A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1983 |
| Grant date | Mar 11, 1986 |
| Priority date | — |
| Expiry date | Dec 7, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/689
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In order to have with an integratable solid state relay a galvanic isolation between the control and the switch similar to that of a mechanical relay the control is performed via DC/DC-converters in a classical voltage-doubler circuit configuration. The switch function is provided by a pair of complementary MOS-transistors (Tr.sub.1 and Tr.sub.2) the gate/source capacitances (C.sub.gs) of which are used as charging capacitances of the DC/DC-converters. In order to have a perfect blocking of the MOS-switches two DC/DC-converters (C.sub.1,C.sub.2,D.sub.1,D.sub.2,C.sub.gs ; C.sub.3,C.sub.2,D.sub.3,D.sub.5,C.sub.gs) are provided which are controlled by two signals in the phase opposition so that for both switching states the same noise margin capability and the same switching-over times result. The circuit arrangement includes only diodes, MOS-transistors and capacitances (C.sub.1,C.sub.2,C.sub.3) of very small value which can be integrated without any difficulties.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.