Arrangement for cancelling the input bias current, at picoampere levels, in an integrated circuit
US4575685A · kind A · utility
12Cited by
1References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 3, 1984 |
| Grant date | Mar 11, 1986 |
| Priority date | — |
| Expiry date | Aug 3, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45479
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An arrangement for cancelling the input bias current, at picoampere levels, in linear integrated circuits such as operational amplifiers, comparators, and the like is disclosed herein. This arrangement utilizes circuitry including a tracking transistor which is virtually independent of the presence or absence of leakage current in the overall integrated circuit, even at relatively high temperatures, for example 125.degree. C., where leakage current can be most significant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.