Electrically alterable non-volatile memory
US4575823A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 17, 1982 |
| Grant date | Mar 11, 1986 |
| Priority date | — |
| Expiry date | Aug 17, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory and method is described incorporating an array of variable threshold transistors, a row decoder, a buffer circuit positioned between the array and row decode circuitry, column decode circuitry, and a sense amplifier. The non-volatile memory overcomes the problem of high voltages in the memory array during READ operation. During READ operation the variable threshold transistors operate in the common source mode. A buffer circuit with level shift capability is described incorporating P and N channel transistors. A sense amplifier with decoupling during sensing or lock out is described incorporating P and N channel transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.