Integrated circuit multilevel interconnect system and method
US4576900A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 11, 1984 |
| Grant date | Mar 18, 1986 |
| Priority date | — |
| Expiry date | Sep 11, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/4847
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming on a substructure a plural layer, conductor interconnect pattern consisting of a plurality of successively formed, substantially planar, composite layers of insulating material and conductive material with said insulating material on each layer defining a pattern of regions filled with conductive material to serve as part of a vertical and horizontal interconnect system. The process includes the following steps for forming each composite layer: PA0 (a) forming a pattern of regions of conductive material on the substructure; PA0 (b) forming over the pattern of conductive regions a layer of insulating material to a thickness substantially greater than the thickness of the conductive material and having a substantially planar top surface; and PA0 (c) removing top surface portions of the layer of insulating material down to the top surface of the regions of conductive material. The step of forming the layer of insulating material includes dispensing onto the wafer a volume of a liquid form of the insulating material to fill gaps between the regions of conductive material and to build up a layer of the insulating material having a substantially planar top surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.