Placement of components on circuit substrates
US4577276A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 1983 |
| Grant date | Mar 18, 1986 |
| Priority date | — |
| Expiry date | Sep 12, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In laying out integrated circuits on a substrate, the placement of the components relative to each other is important in minimizing conductor area and hence chip area. Large scale integration often uses polycells which are lined up in rows to realize the digital logic circuitry. A partitioning procedure is disclosed which iteratively separates the cells into maximally connected subcells, eventually to assign them to rows so as to minimize conductor area. A technique called terminal propagation takes into account at every iteration the location of connections outside of the partitioned area. Rectilinear Steiner trees are generated to aid in terminal propagation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.