Method of manufacturing CMOS devices
US4577391A · kind A · utility
91Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 1984 |
| Grant date | Mar 25, 1986 |
| Priority date | — |
| Expiry date | Jul 27, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0184
Abstract
A CMOS semiconductor structure having insulation sidewall spacers whose width is selected independently for NMOS and PMOS devices. The width of the spacer is selected to reduce hot electron injection in the N channel device and to insure that the gate and source regions are aligned with or underlap the gate in the P channel device. A narrower spacer is used for the P channel device than for the N channel device which permits the formation of a P channel device having a threshold voltage less than 1 volt.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.