System for limiting access to non-volatile memory in electronic postage meters
US4578774A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 18, 1983 |
| Grant date | Mar 25, 1986 |
| Priority date | — |
| Expiry date | Jul 18, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG07B2017/00403
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method and associated apparatus for limiting the erasing and writing of data in the non-volatile memory (NVM) of an electronic postage meter operated under microcomputer control to predetermined periods of time after the power up and during the power down cycles of the meter, comprising the steps and associated apparatus for providing an output power signal in response to the establishment of a power up voltage condition, generating an output pulse in response to the presence of the output power signal, presetting the width of the output pulse to provide sufficient time to erase the desired data words from the NVM, applying a bias enable signal to an NVM enable terminal during the duration of the output pulse, enabling the remaining terminals of the NVM during the duration of the output pulse to allow the erasure of data from the NVM, removing the output power signal in response to a power down voltage condition, interrupting the operation of the microcomputer in response to the removal of the output power signal to ready the microcomputer for writing data in NVM, applying the bias enable signal to the NVM enable terminal at the inception of the power down cycle, enabling the rem…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.