Synchronization circuit for a Viterbi decoder
US4578800A · kind A · utility
Inventors
Key dates
| Filing date | Jul 6, 1983 |
| Grant date | Mar 25, 1986 |
| Priority date | — |
| Expiry date | Jul 6, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0062
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A Viterbi decoder synchronization circuit comprises a phase shifter for introducing a variable amount of delay time to a received bit stream of convolutional codes in response to a control signal applied thereto with respect to a word synchronization signal which is derived from the bit stream. A first detector detects maximum and minimum metric values of the Viterbi decoder. A second detector detects the difference between the detected maximum and minimum metric values for coupling to an integrator. The output of the integrator is applied to a third detector which detects when the integrator output reaches a value indicative of a word-in-sync or word-out-of-sync condition. A phase shift signal is generated in response to an output signal from the third detector and applied to the phase shifter as the control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.