Microprocessor capable of automatically performing multiple bus cycles
US4580213A · kind A · utility
13Cited by
1References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 7, 1982 |
| Grant date | Apr 1, 1986 |
| Priority date | — |
| Expiry date | Jul 7, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4234
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor is disclosed having a bus controller which is capable of automatically performing multiple bus cycles in response to a multi-cycle signal received from the control unit. The bus controller includes means for automatically incrementing the access address provided by the control unit, and for controlling the transfer of the data between the bus and respective destinations in the control units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.