Digital duplex communication system
US4581492A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 15, 1983 |
| Grant date | Apr 8, 1986 |
| Priority date | — |
| Expiry date | Jun 15, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/231
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A digital duplex communication system includes an echo canceller of the look-up table type. The echo canceller has a random access memory (RAM), a digital to analog converter (DAC), a subtractor, adaption means, and an address generator. The echo canceller stores echo replicas for combinations of data bits transmitted by the transmitter and subtracts these echo replicas from a received signal on line before application to the receiver. The capacity required for the RAM is reduced by storing only one echo replica for each of two complementary sets of data. To achieve this the address generator is split into a primary address generator and a complementary address generator so that complementary sets of data present the same address to the RAM. The primary address generator produces a signal to indicate which of the two complementary data sequences is being transmitted and appropriately sets the adaption means over line and a complementing circuit over line. The combination of the signal on line and the output of the subtractor on line causes the echo replica to be updated by the adaption means which may be an adder circuit. The complementing circuit operates on the output of the RAM …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.