TTL tristate device with reduced output capacitance
US4581550A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 1984 |
| Grant date | Apr 8, 1986 |
| Priority date | — |
| Expiry date | Mar 6, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0826
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved TTL tristate device with reduced output capacitance incorporates an active discharge sequence of three elements including first and second active transistor elements (Q8, Q7) in an inversion coupling and a third passive element comprising a passive diode cluster (D3, D4, D5) coupled between the base of the second transistor element (Q7) and the enable gate. The passive diode cluster is operatively arranged for delivering base drive current to the base of the second transistor (Q7) when the enable gate (A) is at high potential for operation of the output device in the bistate mode. The passive diode cluster also operatively diverts base drive current away from the base of the second transistor (Q7) when the enable gate (A) is at low potential for operation of the output device in the high impedance third state with reduced output capacitance. The first transistor element (Q8) of the active discharge sequence coupled to the base of the pull-down transistor element (Q4) follows in phase at its collector the potential maintained by the enable gate (A). It actively conducts, discharges and diverts capacitive feedback Miller current from the base of the pull-down transistor e…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.