Circuit to prevent pirating of an MOS circuit
US4583011A · kind A · utility
51Cited by
4References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 1, 1983 |
| Grant date | Apr 15, 1986 |
| Priority date | — |
| Expiry date | Nov 1, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/903
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and circuit arrangement are disclosed for foiling an attempt to copy an MOS integrated circuit by implementing in the circuit an additional pseudo MOS device, which from its location in the circuit would appear to a would-be copier to be an enhancement-mode device. However, the pseudo-auxiliary MOS device is implemented as a depletion-mode device and is connected in the circuit so that when it is implemented by the copier as an enhancement-mode device. the overall circuit will not be functional.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.