Data processing system wherein all subsystems check for message errors
US4583161A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 1981 |
| Grant date | Apr 15, 1986 |
| Priority date | — |
| Expiry date | Apr 16, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/413
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data processing system employing broadcast packet switching and having a plurality of subsystems and a system bus for linking the subsystems. The subsystems are grouped within stations that are each enclosed by a computer cabinet. The system bus includes a star coupler, first and second external transmission lines connecting each station to the star coupler, and first and second internal transmission lines within each station that are coupled to the first and second external transmission lines. The subsystems within each station are each coupled to the first and second internal transmission lines by a system bus interface. The system bus interface monitors the system bus for an idle condition, and passes a message from its subsystem to the system bus only when it detects an idle condition on the system bus. Each message on the system bus includes a postamble that is garbled by any system bus interface that detects an error in any message on the system bus. Each subsystem has a local memory that includes a mailbox for storing header information of messages that are to be copied by that subsystem. DMA circuitry in each system bus interface manages the operation of the mailbox in it…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.