Digital demodulator arrangement for quadrature signals
US4583239A · kind A · utility
115Cited by
7References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 18, 1984 |
| Grant date | Apr 15, 1986 |
| Priority date | — |
| Expiry date | Oct 18, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0052
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A direct conversion receiver in which the quadrature I and Q signals are converted into pulse density modulated digital data streams by delta-sigma modulators 14, 15. The resultant digital data streams are then processed in a logic block 18 according to predetermined logic truth tables. The digital output of the processor 18 is then converted back to an analogue signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.