Floating point digitizer
US4584560A · kind A · utility
4Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 11, 1984 |
| Grant date | Apr 22, 1986 |
| Priority date | — |
| Expiry date | Jun 11, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/186
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a floating point digitizer, an analog signal is delivered to two signal paths. One includes a delay line. In the first path, the analog signal is measured in terms of order of magnitude to provide a signal indicative of an exponent. This same value is utilized to set the gain of a variable gain amplifier to which the delayed signal is applied and from which a mantissa is resolved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.