Method of residue to analog conversion
US4584562A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 1984 |
| Grant date | Apr 22, 1986 |
| Priority date | — |
| Expiry date | Sep 24, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for accomplishing modulo 2.sup.2n -1 addition with apparatus requiring adders that may be all standard binary adders. The method requires summing binary input signals a and b to produce a first sum signal in which the n+2 more significant bits thereof represent the integer part of a+b taken modulo 2.sup.2n. These n+2 more significant binary bits are subtracted from a 2n bit shifted product representation thereof for producing a first difference signal. This difference signal is subtracted from the first sum signal to produce a binary signal R. When R is greater than or equal to the constant (2.sup.2n -1), this constant is subtracted from the signal R for producing a binary signal that is the first sum signal a+b taken modulo 2.sup.2n -1 .
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.