Residue to analog converter
US4584564A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 1984 |
| Grant date | Apr 22, 1986 |
| Priority date | — |
| Expiry date | Sep 24, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A residue to analog converter associated with residue numbers {m1,m2,m3} of the RNS defined by the moduli set {p1=2.sup.n -1, p2=2.sup.n, p3=2.sup.n +1} comprises a pair of ROMs and a pair of standard binary adders. The first ROM stores a look-up table of summations, taken modulo p1*p2, of possible values of m1*S3 and m3*S1 product terms, where S1=(p1*p2)/2 and S3=(p2*p3)/2, with associated memory locations being addressed by m1 and m3. The first binary adder performs a modulo 2.sup.n summation of a binary signal stored by the first ROM and -m2 by ignoring any overflow. The second ROM stores a look-up table of possible values of the products of p1, p3 and the modulo 2.sup.n signal. The second binary adder sums output signals of the two ROMs for producing a binary signal r(m1,m2,m3) that is representative of the residue signal {m1,m2,m3}. The corresponding analog signal is produced with a standard D/A converter. In an alternate embodiment, look-up tables of possible m1*S3 and m3*S1 product terms are stored in associated ROMs and summed in a modulo p1*p3 adder. In yet another embodiment, the second ROM is replaced with means for bit shifting the modulo p2=2.sup.n signal prior to subt…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.