Parallel-input/serial output CCD register with clocking noise cancellation, as for use in solid-state imagers
US4584609A · kind A · utility
14Cited by
5References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 15, 1985 |
| Grant date | Apr 22, 1986 |
| Priority date | — |
| Expiry date | Apr 15, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/745
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Alternate ones of the charge transfer stages in the CCD output register of a solid-state imager are loaded with charge packets descriptive of the intensities of respective image elements. The intervening charge transfer stages are loaded with charge packets descriptive of a reference level. Subsequently, the CCD output register is operated as a shift register to serially supply charge packets to an electrometer. Successive samples of the electrometer response are differentially combined to obtain an output signal with undesired components suppressed therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.