Method for manufacturing a gate array integrated circuit device
US4584653A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Mar 22, 1983 |
| Grant date | Apr 22, 1986 |
| Priority date | — |
| Expiry date | Mar 22, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a gate array IC device in which the turn-around time on design is short, the system design is simple, and the memory area for designing is reduced. The method includes manufacturing a master bulk pattern of a basic cell array on the semiconductor substrate, and storing, in semi-permanent memory, symbol data and detailed data for standard macro cells and standard expanded macro cells prior to designing a logic system. Each macro cell comprises one or more basic cells and has a basic logic function. Each expanded macro cell comprises plural macro cells and has a more complicated and sophisticated logic function than the macro cells. In addition, the logic functions of the expanded macro cells are standard in the logic system design technology area. When a designer creates a logic system, only symbol data for the macro cells and the expanded macro cells, and the connections thereof are used and stored in the memory, so that it is relatively easy to design the system. Actual conductive wiring patterns are synthesized from the logic system data and the detailed data; consequently these patterns are produced on the semiconductor substrate which is already provi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.