Digital PLL decoder
US4584695A · kind A · utility
86Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1983 |
| Grant date | Apr 22, 1986 |
| Priority date | — |
| Expiry date | Nov 9, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital PLL technique to provide an effective sampling interval and resolution shorter than the driver clock period. A multi-phase driver clock provides a clock signals phase-offset from each other. One clock output signal is used as the driver clock to clock an input sampler. A pattern of bit samples before, nominally at, and after a predicted clock edge indicates whether a leading or lagging phase should be substituted for the present driver clock signal. The phase difference is substantially less than the period of the fastest clock presently available to generate satisfactory shaped pulses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.