IC chip with noise suppression circuit
US4585958A · kind A · utility
17Cited by
8References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1983 |
| Grant date | Apr 29, 1986 |
| Priority date | — |
| Expiry date | Dec 30, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A microprocessor chip is adapted to maintain its databus at a reference voltage level during idle times between outputs. The arrangement enables like pull-up and pull-down delays as well as low noise levels to be achieved in the output circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.