Semiconductor integrated circuit for squaring a signal with suppression of the linear component
US4585961A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 19, 1984 |
| Grant date | Apr 29, 1986 |
| Priority date | — |
| Expiry date | Jan 19, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit for squaring an original input signal includes a pair of dual-ended difference amplifiers to each of which the input signal is delivered, a pair of dual-to-single-ended converters, each receiving the respective dual-ended output of the respective difference amplifier, and a summing network for summing the squares of the outputs of the dual-to-single-ended converters. One of the dual-to-single-ended converters receives the dual-ended output of the corresponding dual-ended amplifier in opposite (cross-coupled) order from that of the other, whereby the output of the summing network is, except for an additive constant, proportional to the square of the original input signal independently of power supply voltage fluctuations within reasonable limits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.