Interface circuit for signal generators with two non-overlapping phases
US4587441A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1983 |
| Grant date | May 6, 1986 |
| Priority date | — |
| Expiry date | Oct 13, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09445
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interface circuit with MOS-type transistors for timing signal generators with two non-overlapping phases made up of two identical twin circuits, each having a final stage of the type including two transistors connected in series between the two terminals of a supply voltage generator and a bootstrap capacitor. Each of the two twin circuits includes a logic NOR circuit and a logic AND circuit which control, respectively, the charging and discharging of the capacitor through a suitable switching circuit connected to both terminals thereof. In each circuit, a memory circuit element is connected to the logic circuits. The memory circuit element is sensitive to the output signals of both twin circuits and enables the charging and discharging of the bootstrap capacitor at successive, logically produced time intervals which occur between the pulses of the output signals of both twin circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.