System for generating circuit boards using electroeroded sheet layers
US4587727A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 5, 1983 |
| Grant date | May 13, 1986 |
| Priority date | — |
| Expiry date | Jul 5, 2003 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49126
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
By use of an electroerosion technique a plurality of conductive lines (5) are isolated out of an electrically conductive sheet material supported on an isolating substrate of a sheet having holes in a distinct pattern. Several sheets are superimposed in different planes and are alternately mixed with interplane spacer-connector layers between a terminal block (32) and a pressing guide block. The interplane spacer-connector layer (24) contains contact areas interconnected with each other and make contact with isolated zones in different superimposed planes of sheets. The terminal block is provided with sockets for holding the terminals of circuit components of the to-be-developed electrical circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.