Integrated digital MOS semiconductor circuit

US4588907A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Willibald Meyer · Hersbruck, DE
• Jurgen Warwersig · Munich, DE

Key dates

• Filing date: May 14, 1984
• Grant date: May 13, 1986
• Expiry date: May 14, 2004

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C29/46
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

For integrated digital MOS semiconductor circuits having redundant circuit parts, particularly for semiconductor memories having redundant rows and columns, it is desirable after the employment of the redundant circuit parts to be able to distinguish such a module from those modules in which such an employment of redundant circuit parts has not yet occurred. According to the invention, signals are enabled which serve for the normal mode as well as for the test mode to be input into the circuit via the same signal input. Test signals are distinguished from the other signals by an elevated signal level. The circuit according to the invention includes a circuit part to be activated by means of interrupting a conductive connection, said circuit part then distinguishing the signals applied to the input from one another on the basis of their levels and generating secondary signals on the basis of the signals having the elevated level, said secondary signals then being provided for the control of the test mode.