Digital adder including counter coupled to individual bits of the input
US4589019A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1983 |
| Grant date | May 13, 1986 |
| Priority date | — |
| Expiry date | Apr 22, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An adder circuit is described for producing signals representative of the sum of large numbers of block-synchronized digital signals each of which may have any value within the range of quantizing levels represented. The adder circuit includes one or more binary counters coupled to count bits of the input signal having a particular significance. Counting takes place during an active interval such as a television field interval, and the counters are reset after each counting interval. The counter outputs are latched either before or after processing by addition of other counter outputs. The latched signal represents the sum of the values of the words in one sync block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.