Mechanism for implementing one machine cycle executable trap instructions in a primitive instruction set computing system
US4589065A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1983 |
| Grant date | May 13, 1986 |
| Priority date | — |
| Expiry date | Jun 30, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism for performing a run-time storage address validity check within one machine cycle. The mechanism, functioning together with an intelligent compiler, eliminates the need for hardware implementation of a storage validity check. More particularly, the mechanism performs its function in one machine cycle in the event that a trap exception does not cause an interrupt. In the rare instance when an interrupt is necessary, a number of machine cycles will be impacted. The mechanism comprises a minimum amount of logic circuitry for determining the trap condition operating in conjunction with conventional, previously existing compare, branch instruction testing, and interrupt generation circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.