Full floating point vector processor with dynamically configurable multifunction pipelined ALU
US4589067A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 1983 |
| Grant date | May 13, 1986 |
| Priority date | — |
| Expiry date | May 27, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3895
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A full floating point vector processor includes a master processing unit having DMA I/O means, a wide bandwidth data memory having static RAM and/or interleaved dynamic RAM, an address generator operative to provide address generation for data loaded in the data memory, a concurrently operating pipeline control sequencer operative to provide fully programmable horizontal format microinstructions synchronously with the addresses generated by the address generator, and a pipelined arithmetic and logical unit responsive to the addressed data and to the synchronously provided microinstructions and operative to evaluate one of a user selectable plurality of computationally intensive functions. The address generator, the pipeline controlsequencer, and the master processing unit are configured in parallel. The address generator includes means operative to provide pipeline input and output data dependent address generation. The microinstruction controlled pipelined arithmetic and logical unit includes two register files controllably interconnectable over feedforward and feedback data flow paths, a user selectable fixed or floating point format multiplier, a user selectable fixed or floatin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.