Data processing system
US4589086A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 1982 |
| Grant date | May 13, 1986 |
| Priority date | — |
| Expiry date | Aug 30, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/523
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system having an arithmetic unit is designed for a multiplication of n-place numbers in 2's complement according to the Booth algorithm, and for division of unsigned numerals. A 2n-stage shift register is connected over a logical control circuit to the operation code inputs of an ALU. The control circuit automatically forms instruction code signals to the ALU as a function of informational bits derived from the shift register, whereas other operation code input signals are directly connected to the operation code inputs. The control circuit is a sequential circuit having a multiplexer for the selective through-connection of the multiplication code signals, the division code signals, or other operation code signals to the operation code inputs of the ALU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.