Digital gain adjuster circuit for photomultiplier tubes
US4590368A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 22, 1983 |
| Grant date | May 20, 1986 |
| Priority date | — |
| Expiry date | Feb 22, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J43/30
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A gain adjuster circuit is disclosed for adjusting the gain of a plurality of photomultiplier tubes (PMT's) by digital circuitry. The circuit includes a plurality of PMT's, each having a specific internal resistance. A plurality of switches and resistances are connected in series with the PMT's. The digital circuitry is designed for adjusting the effective resistances thereof, to adjust thereby the voltage across each of the several PMT's. Preferably, the digital circuitry includes a demultiplexer coupled, via the switches and resistances, to the PMT's, a flip-flop coupled to the demultiplexer, and a presettable counter coupled to the flip-flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.