Low leakage CMOS D/A converter
US4590456A · kind A · utility
17Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 6, 1985 |
| Grant date | May 20, 1986 |
| Priority date | — |
| Expiry date | Aug 6, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/785
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS DAC with means to avoid leakage current. In one embodiment, the back gates of the CMOS switches are held at -200 mV with respect to the output lines, and the logic low level to the off switch also is set at -200 mV relative to the output lines. In another embodiment, the CMOS switches are ion-implanted. In a still further embodiment, the output lines are held at a potential 200 mV more positive than the P- well of the CMOS switches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.