Graphics display system using logic-enhanced pixel memory cells
US4590465A · kind A · utility
Inventor
Key dates
| Filing date | Feb 18, 1982 |
| Grant date | May 20, 1986 |
| Priority date | — |
| Expiry date | Feb 18, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/42
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a relatively inexpensive raster-scan type graphics system capable of real time operation, utilizing logic-enhanced pixels within an image buffer, permitting parallel (simultaneous) calculations at every pixel. A typical implementation would be as custom VLSI chips. In the sequence of most general applications, each polygon is operated upon in sequence, and the image is built up as the polygons are processed without the necessity of sorting. With respect to each successive polygon, the following operations are effected: (1) all pixels within the polygon are identified; (2) the respective pixels which would be visible to the observer, that is, not obstructed by some previously processed polygon, are determined; and (3) the proper color intensities for each visible pixel are determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.