Co-processor combination
US4590556A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 1983 |
| Grant date | May 20, 1986 |
| Priority date | — |
| Expiry date | Jan 17, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual processor system in which one processor is dedicated to input/output tasks while the other is dedicated to high level language tasks when operating as a 16-bit machine. The processors include a first microprocessor which is an 8-bit machine, and a second microprocessor which is a 16-bit machine. The first processor has a memory associated therewith which may, for example, be a 64K memory while the second processor has a larger capacity memory. The second processor does not access the memory of the first processor, however, the first processor can access a portion of the second processor's memory. Access to the second processor's memory is controlled by an arbitrator that is operated by system software to prevent access conflicts. For boot-up during power-up operation, a boot ROM is used, attached to the 8-bit processor having stored therein a boot strap program that is initially loaded into the 8-bit processor memory. If the operating system loaded from a diskette indicates 8-bit software, then the 16-bit processor is maintained reset or halted. On the other hand, if the operating system is a 16-bit system, then the boot program loads the 16-bit memory making the 16-bit proc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.