Latch for storing a data bit and a store incorporating said latch
US4592023A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 1984 |
| Grant date | May 27, 1986 |
| Priority date | — |
| Expiry date | Jun 21, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A latch that can serve as a bit storage cell in a random-access store. The latch includes an AND gate (diodes D1 and D2) the input IN of which receives the bit to be stored and the other input of which is connected to a write control line WRL. When no write operation is being performed, transistor T1 is turned off and the state of transistor T2 is dependent on output potential OUT. To perform a write operation, line WRL is activated (goes high) and the state of transistor T3 will depend on the value of the bit applied to input IN. Read operations are performed by means of another AND gate (diodes D4 and D5) and an emitter follower (transistor T4) connected via a bit line BL to an output circuit 2. By adding input transistors and emitter followers to the latch, a multi-port storage can be realized, several rows of which can be simultaneously written into and/or read out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.