Memory device
US4592028A · kind A · utility
15Cited by
0References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 8, 1983 |
| Grant date | May 27, 1986 |
| Priority date | — |
| Expiry date | Jun 8, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1534
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device such as a random-access memory in which in response to an input signal such as an address signal, two signals having the opposite logical relationship with each other generated from the input signal and delayed with respect to the input signal are applied to a detector for detecting the transition of the input signal, whereby address transition detector signal having normal time relationship with the address signal can be obtained even when the address signal changes very slowly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.