Process for fabricating multi-level-metal integrated circuits at high yields
US4592132A · kind A · utility
15Cited by
5References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1984 |
| Grant date | Jun 3, 1986 |
| Priority date | — |
| Expiry date | Dec 7, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Inter-layer electrical shorting between layers of conductors of an integrated circuit caused by "hillocks" in the bottom layer is prevented by the use of a double layer photoresist coatings atop the insulating layer that separates the metal layers. The double layer photoresist insures that irregularities in the dielectric layer caused by hillocks in the underlying insulating layer do not cause a break in the photoresist and a subsequent undesired etching of a spurious "via" through the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.