Heterostructure bipolar transistor

US4593305A · kind A · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Mamoru Kurata · Tokyo, JP
• Jiro Yoshida · Tokyo, JP

Key dates

• Filing date: May 8, 1984
• Grant date: Jun 3, 1986
• Expiry date: May 8, 2004

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/084

Abstract

A heterostructure bipolar transistor has an emitter layer, a base layer and a collector layer, the emitter layer being formed of a semiconductor material whose energy gap is wider than that of the base layer, so that a heterojunction is formed between the emitter layer and the base layer. One of the emitter layer and the base layer has first and second layers which are sequentially formed, and the first layer constituting the heterojunction has a lower impurity concentration than that of the second layer. When the impurity concentration and the thickness of the first layer are defined as N.sub.1 and W.sub.1, respectively, the following relation is satisfied: EQU N.sub.1 W.sub.1.sup.2 .ltoreq.(2.epsilon..sub.s .epsilon..sub.0 /q)V.sub.bi where PA1 q: the absolute value of electron charge PA2 (=1.6.times.10.sup.-19 Coulombs), PA1 .epsilon..sub.0 : the free space permittivity PA2 (=8.86.times.10.sup.-14 farads/cm), PA1 .epsilon..sub.s1 : the dielectric constant of the first layer, and PA1 V.sub.bi : the built-in potential at the heterojunction.