Quasi parallel cyclic redundancy checker
US4593393A · kind A · utility
34Cited by
12References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 6, 1984 |
| Grant date | Jun 3, 1986 |
| Priority date | — |
| Expiry date | Feb 6, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for operating a CRC in a parallel, quasi parallel or serial fashion. The device allows all the bits in a word to be read and loaded into the cyclic redundancy checker (CRC) register in one clock cycle putting it in sync with the rest of the system. The CRC consists of a set of logic gates for converting a parallel input signal to a converted parallel input signal that is the equivalent of the conversion performed on the serial data input into the prior art cyclic redundancy checkers. The bits of the converted parallel input signal are then combined in another set of logic gates to provide the CRC output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.