Digital parallel computing circuit for computing p=xy+z in a shortened time
US4594678A · kind A · utility
23Cited by
3References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 10, 1983 |
| Grant date | Jun 10, 1986 |
| Priority date | — |
| Expiry date | Feb 10, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To increase the computing speed when forming the product of a first binary number (x) and a second binary number (y) and then adding (xy+z) a third binary number (z) by means of a multiplier (mw) and an adder (aw), the individual full-adder stages of the adder (aw) except the stage for the sign digit are inserted as an additional row between the next to the last row and the output row of the multiplier, the full-adder for the sign digit of the output row (az) being also omitted. The two omitted stages are replaced with a sign-correcting stage (vk).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.