Alignment correction technique
US4595836A · kind A · utility
1Cited by
6References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 29, 1984 |
| Grant date | Jun 17, 1986 |
| Priority date | — |
| Expiry date | Jun 29, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R19/0038
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An E-beam alignment correction system employing an up-up integration technique. Input signals during each scan period are integrated and digitized then held in respective registers. The value in one register is converted to its negative value then digitally combined with the other value to generate an alignment correction value. This technique eliminates the requirement of positive and negative integrations needed with up-down integration techniques and droop of the sample and hold device as a function of time. A common analog path is used so that errors add out during digital combination of signal values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.