Data processing technique for computer color graphic system
US4595917A · kind A · utility
14Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 1983 |
| Grant date | Jun 17, 1986 |
| Priority date | — |
| Expiry date | Jun 13, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/022
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A frame buffer, divided into three bit planes, is addressed by a single grahic display control chip, whose address signal is altered by an adder to address each bit plane at successive, prescribed time intervals during a single display cycle. A data word of N-bits from each of the first two bit planes is read and latched, then loaded simultaneously with a data word of N-bits from the third bit plane into corresponding shift registers. Thus, the number of memory chips in the frame buffer is minimized and three times the normal data output is achieved during each display cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.