Patent · US Expired

For the protection of an MOS-transistor from overloading

US4595966A · kind A · utility

13Cited by
2References
5Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 2, 1983
Grant dateJun 17, 1986
Priority date
Expiry dateNov 2, 2003

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03K17/0822
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

An arrangement for the protection of a transistor, particularly a MOS-switching transistor including a zener diode connected between the gate and source terminals for limiting the gate potential and a switch-off transistor connected to the control circuit of the MOS-transistor for grounding the gate thereof and switching it off. First and second monitoring circuits are coupled between the MOS-transistor and the switch-off transistor for producing a signal switching on the switch-off transistor in response to a drop in the load current and an increase in the output voltage of the MOS-transistor. First and second timing circuits block the signals of the monitoring circuits for predetermined intervals.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.