High speed memory with a multiplexed address bus
US4596004A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 1983 |
| Grant date | Jun 17, 1986 |
| Priority date | — |
| Expiry date | Sep 14, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory access time, noise and costs are substantially reduced while reliability is increased by replacing fixed delay lines with a dynamic delay. This dynamic delay is placed on the same integrated circuit as the remainder of the memory access circuitry to eliminate tracking problems associated with off-chip delay lines. The dynamic delay element is activated after all of the row address strobe (RAS) bits have been generated. These RAS bits serve to strobe the row column address bits initially present on the address bus into the memory. After the delay time has elapsed an address multiplexor switches column address bits onto the address bus to replace the prior row address bits. As soon as this switch is completed column address strobe (CAS) bits are generated to strobe the column address bits into the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.