Etching a layer over a semiconductor
US4596627A · kind A · utility
2Cited by
1References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 1985 |
| Grant date | Jun 24, 1986 |
| Priority date | — |
| Expiry date | Jun 13, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new phenomenon in integrated circuit etch processing is presented, explained and utilized to permit better removal of layers overlying integrated circuit structures, and if desired, the formation of conductive layers on such structures by a less complicated and lower temperature process than has been possible by conventional techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.